`timescale 1ns / 1ps

module timer(
    input msc,
    input set,
    output [6:0]ms,
    output [5:0]s,
    output [6:0]m
    );
    reg [6:0]msr=7'b0;
    reg [5:0]sr=6'b0;
    reg [6:0]mr=7'b0;
    
    //carry flag
    reg ms_flag=0;
    reg s_flag=0;
    
    //3 mods
    //00 - clear
    //01 - timing
    //10 - stop
    reg [1:0]mode=2'b00;
    reg msc_r;

    //mode counter
    always @ (posedge set) begin
        if (mode==2'b10) mode<=2'b00;
        else mode <= mode + 1;
    end

    //block clock at mod00 &mod11
    always @ (mode[0] or msc) begin
        if (mode[0]==1) msc_r=msc;
        else msc_r=0;
    end

    //ms counter
    always @ (posedge msc_r or negedge mode[1]) begin
        if(msr == 7'd99) begin
            msr<=7'd0;
            ms_flag <= 1;
        end
        else begin
            msr <= msr + 1;
            ms_flag <= 0;
        end
        if(mode[1]==0 && mode[0]==0) begin //clear in mod00
            msr <= 0;
            ms_flag <= 0;
        end
    end

    //second counter
    always @ (posedge ms_flag or negedge mode[1]) begin
        if(sr == 6'd59) begin
            sr<=6'd0;
            s_flag <= 1;
        end
        else begin
            sr <= sr+1;
            s_flag <= 0;
        end
        if(mode[1]==0 && mode[0]==0) begin //clear in mod00
            sr <= 0;
            s_flag <= 0;
        end
    end

    //minuit counter
    always @ (posedge s_flag or negedge mode[1]) begin
        if(mr == 7'd99) mr<=7'd0;
        else mr <= mr+1;
        if(mode[1]==0 && mode[0]==0) mr <= 0; //clear in mod00
    end

    assign ms = msr;
    assign s = sr;
    assign m = mr;
endmodule

module changer(
    input [7:0]src,
    output [3:0]ten,
    output [3:0]one
);
    reg [3:0]t_r;
    reg [3:0]o_r;
    always @ (src)
    begin
    case(src)
        7'b0000000: begin t_r <= 4'd0; o_r <= 4'd0; end
        7'b0000001: begin t_r <= 4'd0; o_r <= 4'd1; end
        7'b0000010: begin t_r <= 4'd0; o_r <= 4'd2; end
        7'b0000011: begin t_r <= 4'd0; o_r <= 4'd3; end
        7'b0000100: begin t_r <= 4'd0; o_r <= 4'd4; end
        7'b0000101: begin t_r <= 4'd0; o_r <= 4'd5; end
        7'b0000110: begin t_r <= 4'd0; o_r <= 4'd6; end
        7'b0000111: begin t_r <= 4'd0; o_r <= 4'd7; end
        7'b0001000: begin t_r <= 4'd0; o_r <= 4'd8; end
        7'b0001001: begin t_r <= 4'd0; o_r <= 4'd9; end
        7'b0001010: begin t_r <= 4'd1; o_r <= 4'd0; end
        7'b0001011: begin t_r <= 4'd1; o_r <= 4'd1; end
        7'b0001100: begin t_r <= 4'd1; o_r <= 4'd2; end
        7'b0001101: begin t_r <= 4'd1; o_r <= 4'd3; end
        7'b0001110: begin t_r <= 4'd1; o_r <= 4'd4; end
        7'b0001111: begin t_r <= 4'd1; o_r <= 4'd5; end
        7'b0010000: begin t_r <= 4'd1; o_r <= 4'd6; end
        7'b0010001: begin t_r <= 4'd1; o_r <= 4'd7; end
        7'b0010010: begin t_r <= 4'd1; o_r <= 4'd8; end
        7'b0010011: begin t_r <= 4'd1; o_r <= 4'd9; end
        7'b0010100: begin t_r <= 4'd2; o_r <= 4'd0; end
        7'b0010101: begin t_r <= 4'd2; o_r <= 4'd1; end
        7'b0010110: begin t_r <= 4'd2; o_r <= 4'd2; end
        7'b0010111: begin t_r <= 4'd2; o_r <= 4'd3; end
        7'b0011000: begin t_r <= 4'd2; o_r <= 4'd4; end
        7'b0011001: begin t_r <= 4'd2; o_r <= 4'd5; end
        7'b0011010: begin t_r <= 4'd2; o_r <= 4'd6; end
        7'b0011011: begin t_r <= 4'd2; o_r <= 4'd7; end
        7'b0011100: begin t_r <= 4'd2; o_r <= 4'd8; end
        7'b0011101: begin t_r <= 4'd2; o_r <= 4'd9; end
        7'b0011110: begin t_r <= 4'd3; o_r <= 4'd0; end
        7'b0011111: begin t_r <= 4'd3; o_r <= 4'd1; end
        7'b0100000: begin t_r <= 4'd3; o_r <= 4'd2; end
        7'b0100001: begin t_r <= 4'd3; o_r <= 4'd3; end
        7'b0100010: begin t_r <= 4'd3; o_r <= 4'd4; end
        7'b0100011: begin t_r <= 4'd3; o_r <= 4'd5; end
        7'b0100100: begin t_r <= 4'd3; o_r <= 4'd6; end
        7'b0100101: begin t_r <= 4'd3; o_r <= 4'd7; end
        7'b0100110: begin t_r <= 4'd3; o_r <= 4'd8; end
        7'b0100111: begin t_r <= 4'd3; o_r <= 4'd9; end
        7'b0101000: begin t_r <= 4'd4; o_r <= 4'd0; end
        7'b0101001: begin t_r <= 4'd4; o_r <= 4'd1; end
        7'b0101010: begin t_r <= 4'd4; o_r <= 4'd2; end
        7'b0101011: begin t_r <= 4'd4; o_r <= 4'd3; end
        7'b0101100: begin t_r <= 4'd4; o_r <= 4'd4; end
        7'b0101101: begin t_r <= 4'd4; o_r <= 4'd5; end
        7'b0101110: begin t_r <= 4'd4; o_r <= 4'd6; end
        7'b0101111: begin t_r <= 4'd4; o_r <= 4'd7; end
        7'b0110000: begin t_r <= 4'd4; o_r <= 4'd8; end
        7'b0110001: begin t_r <= 4'd4; o_r <= 4'd9; end
        7'b0110010: begin t_r <= 4'd5; o_r <= 4'd0; end
        7'b0110011: begin t_r <= 4'd5; o_r <= 4'd1; end
        7'b0110100: begin t_r <= 4'd5; o_r <= 4'd2; end
        7'b0110101: begin t_r <= 4'd5; o_r <= 4'd3; end
        7'b0110110: begin t_r <= 4'd5; o_r <= 4'd4; end
        7'b0110111: begin t_r <= 4'd5; o_r <= 4'd5; end
        7'b0111000: begin t_r <= 4'd5; o_r <= 4'd6; end
        7'b0111001: begin t_r <= 4'd5; o_r <= 4'd7; end
        7'b0111010: begin t_r <= 4'd5; o_r <= 4'd8; end
        7'b0111011: begin t_r <= 4'd5; o_r <= 4'd9; end
        7'b0111100: begin t_r <= 4'd6; o_r <= 4'd0; end
        7'b0111101: begin t_r <= 4'd6; o_r <= 4'd1; end
        7'b0111110: begin t_r <= 4'd6; o_r <= 4'd2; end
        7'b0111111: begin t_r <= 4'd6; o_r <= 4'd3; end
        7'b1000000: begin t_r <= 4'd6; o_r <= 4'd4; end
        7'b1000001: begin t_r <= 4'd6; o_r <= 4'd5; end
        7'b1000010: begin t_r <= 4'd6; o_r <= 4'd6; end
        7'b1000011: begin t_r <= 4'd6; o_r <= 4'd7; end
        7'b1000100: begin t_r <= 4'd6; o_r <= 4'd8; end
        7'b1000101: begin t_r <= 4'd6; o_r <= 4'd9; end
        7'b1000110: begin t_r <= 4'd7; o_r <= 4'd0; end
        7'b1000111: begin t_r <= 4'd7; o_r <= 4'd1; end
        7'b1001000: begin t_r <= 4'd7; o_r <= 4'd2; end
        7'b1001001: begin t_r <= 4'd7; o_r <= 4'd3; end
        7'b1001010: begin t_r <= 4'd7; o_r <= 4'd4; end
        7'b1001011: begin t_r <= 4'd7; o_r <= 4'd5; end
        7'b1001100: begin t_r <= 4'd7; o_r <= 4'd6; end
        7'b1001101: begin t_r <= 4'd7; o_r <= 4'd7; end
        7'b1001110: begin t_r <= 4'd7; o_r <= 4'd8; end
        7'b1001111: begin t_r <= 4'd7; o_r <= 4'd9; end
        7'b1010000: begin t_r <= 4'd8; o_r <= 4'd0; end
        7'b1010001: begin t_r <= 4'd8; o_r <= 4'd1; end
        7'b1010010: begin t_r <= 4'd8; o_r <= 4'd2; end
        7'b1010011: begin t_r <= 4'd8; o_r <= 4'd3; end
        7'b1010100: begin t_r <= 4'd8; o_r <= 4'd4; end
        7'b1010101: begin t_r <= 4'd8; o_r <= 4'd5; end
        7'b1010110: begin t_r <= 4'd8; o_r <= 4'd6; end
        7'b1010111: begin t_r <= 4'd8; o_r <= 4'd7; end
        7'b1011000: begin t_r <= 4'd8; o_r <= 4'd8; end
        7'b1011001: begin t_r <= 4'd8; o_r <= 4'd9; end
        7'b1011010: begin t_r <= 4'd9; o_r <= 4'd0; end
        7'b1011011: begin t_r <= 4'd9; o_r <= 4'd1; end
        7'b1011100: begin t_r <= 4'd9; o_r <= 4'd2; end
        7'b1011101: begin t_r <= 4'd9; o_r <= 4'd3; end
        7'b1011110: begin t_r <= 4'd9; o_r <= 4'd4; end
        7'b1011111: begin t_r <= 4'd9; o_r <= 4'd5; end
        7'b1100000: begin t_r <= 4'd9; o_r <= 4'd6; end
        7'b1100001: begin t_r <= 4'd9; o_r <= 4'd7; end
        7'b1100010: begin t_r <= 4'd9; o_r <= 4'd8; end
        7'b1100011: begin t_r <= 4'd9; o_r <= 4'd9; end
    endcase
    end
    assign ten = t_r;
    assign one = o_r;
endmodule